1. Field of the Invention
The present invention relates to the semiconductor field, and more specifically relates to a semiconductor device and a method for manufacturing a semiconductor device.
2. Description of the Related Art
With the increasing development of semiconductor techniques, further improvement in packaging technology of semiconductor integrated device is demanded. Through Substrate Via (TSV) technology is a new packaging technology used for packaging different chips together, in which a via through the substrate and filled with a conductive material is formed, and then a plurality of chips or wafers are bonded together in a stacked manner thereby achieving an electrical connection between chips by using the via. TSV technology can combine chips of different functions together, increase the stacking density of chips in a three-dimensional direction, reduce the product size of an integrated circuit (IC), and significantly improve the operating speed and reduce the power consumption of chips.
TSV process can be integrated into different stages of the manufacturing process.
One common scheme is that the TSV process is performed before the formation of a functional structure (e.g., metal oxide semiconductor (MOS) transistor) on the substrate. For example, before forming the functional structure, a hole is formed by etching from a side of the substrate on which the functional structure is to be formed, and then the hole is filled with a conductive material. Then the functional structure is formed on the substrate; before stacking chips or wafers, the substrate is thinned such that the hole penetrates there through, thereby obtaining a via that penetrates through the substrate and is filled with the conductive material. However, if the TSV is filled with metal, contamination usually occurs on the substrate which makes a great impact on the subsequent process. Besides, the metal filling the hole cannot endure the high temperature during the formation of the functional structure, such as the high temperature for conducting a thermal oxidation process for forming a gate dielectric layer, or the high temperature for conducting a source/drain region activation process. On the other hand, if the TSV is filled with poly-silicon, the conductive performance of the TSV will deteriorate due to the high resistance of the poly-silicon.
The TSV process can also be performed in other stages. For example, the TSV process can start after the formation of the functional structure (such as MOS transistor) but before the back-end-of-line (BEOL) process (such as an interconnect process). Nevertheless, in this scheme, after the hole is filled with the conductive material, difficulty in the chemical mechanical polishing (CMP) process exists because the functional structure has been formed on the substrate. In another example, the TSV process can be performed after the BEOL process but before the bonding of the wafers. However, in this scheme, the area of the wafer usually has to be increased, so as to keep sufficient space for the TSV process after the interconnect process, and the complexity of the interconnect process is also raised. In yet another example, the TSV process can be performed after the bonding of the wafers. However, the disadvantage brought in by this scheme is that the bonding material utilized for bonding the wafers is usually damaged due to the inability to bear the high temperature during the TSV process, so that the wafers cannot be bonded together.
A TSV process is disclosed in US patent application publication No. 2010/0093169A1, which is titled “Through Substrate Via Process” and published on Apr. 15, 2010. In this disclosure, before forming a functional structure on a first side of a substrate, a hole is formed at the first side with a layer of a first dielectric material formed on a sidewall and a bottom of the hole as an isolation layer and is filled with a second dielectric material, wherein the first dielectric material and the second dielectric material are different from each other and can respectively be one of silicon oxide and silicon nitride. Then the functional structure is formed on the substrate; thereafter, the substrate is thinned from the backside (opposite to the first side) of the substrate to expose the second dielectric material in the hole, the second dielectric material in the hole is removed, and then the hole is filled with a metal (e.g. copper), so as to obtain a final TSV with metal filled therein. In this scheme, before forming the functional structure, the material filling the hole of the substrate is a dielectric material like silicon oxide or silicon nitride instead of a metal, which is not damaged by will not contaminate the substrate. In addition, the above-mentioned problems in the case when the TSV process is performed after the formation of the functional structure can be avoided.
For the convenience of discussion, in the following description, the material that temporarily fills the hole before filling the hole with the final TSV filling material (e.g., copper) during the TSV fabrication is referred to as the “TSV dummy material”.